A programmable logic device (PLD) is a general-purpose device that can be programmed by a user to implement a variety of selected functions. One type of PLD is the Field Programmable Gate Array (FPGA), which typically includes an array of configurable logic blocks (CLBs) surrounded by a plurality of input/output blocks (IOBs). The CLBs are individually programmable and can be configured to perform a variety of logic functions on a few input signals. The IOBs can be configured to drive output signals from the CLBs to external pins of the FPGA and/or to receive input signals from the external FPGA pins. The FPGA also includes a programmable interconnect structure that can be programmed to selectively route signals among the various CLBs and IOBs to produce more complex functions of many input signals. The CLBs, IOBs, and the programmable interconnect structure are programmed by loading configuration data into associated memory cells that control various switches and multiplexers within the CLBs, IOBs, and the interconnect structure to implement logic and routing functions specified by the configuration data. The configuration data is typically stored in an external non-volatile memory device such as a PROM or flash memory device and provided to the FPGA during well-known configuration operations.
An FPGA includes a plurality of generic resources (e.g., programmable logic blocks) that are configurable to implement various user designs, and many user designs may not utilize all the resources of the FPGA. As a result, an FPGA configured to implement a given function typically has a higher fabrication cost than an ASIC device that is specifically designed to perform the same function. Therefore, when sales of a system including an FPGA that is configured to implement a specified function reach a point where it becomes more economical to produce dedicated devices specifically tailored to perform the specified function, the FPGAs in the system may be replaced with a dedicated device that implements the same function and has the same pin-outs, timing characteristics, and performance metrics of the replaced FPGA.
For example, U.S. Pat. No. 5,550,839 entitled “Mask-Programmed Integrated Circuits Having Timing and Logic Compatibility to User-Configured Logic Arrays”, which is incorporated herein by reference in its entirety and which is assigned to the assignee of the present invention, describes a dedicated device that is a pin, timing, and performance compatible replacement for an FPGA device. The dedicated device, which is commercially available as the Hardwire™ device from Xilinx, Inc. and is further described in the “Hardwire Data Book” published in 1994 by Xilinx, Inc., is a mask-programmable logic device that is capable of performing the same logical functions as a software programmable IC device such as an FPGA or PLD. More specifically, the mask programmable IC device includes many processing layers. The first several layers, which form individual device resources such as CLBs, IOBs, and the like, are common to both the FPGA devices and to the mask-programmable IC devices. The several top layers, which may include some metal layers, via layers, and contact layers, define the specific functions performed by a corresponding mask-programmed IC device, thereby “programming” the IC device to implement a user-specified function. Thus, a “programmed Hardwire device” is a Hardwire device that has been processed to add the programmable mask layers that define a specific design or function to be implemented.
Ideally, a Hardwire device can emulate the FPGA it replaces in all respects so that replacing the FPGA with the Hardwire device is transparent to the system and its users. A method used by Xilinx, Inc. to produce one type of Hardwire device includes virtually duplicating the architecture of the FPGA to be replaced, but replacing the software-programmable configuration memory cells with mask-programmable (e.g., hardwire) connections. Eliminating the configuration memory cells significantly reduces the required silicon area, and therefore also reduces manufacturing costs. Further, making the devices mask programmable allows much of the design and processing to be done only once for each FPGA product. Top-level processing layers specific to the user's design are then added to customize the behavior of the Hardwire device to match the functional behavior of the emulated FPGA as configured in the user's system.
Although effective in allowing FPGAs to be replaced by less-expensive Hardwire devices, the design process used to match the timing and performance characteristics of the Hardwire device with that of the emulated FPGA involves a relatively high development cost. Further, as the number of functional gates provided within FPGA devices increases, the cost savings realized by eliminating the configuration memory cells becomes less significant. Indeed, for current FPGA devices having millions of gates, the costs associated with designing the Hardwire device may exceed the cost savings realized by eliminating the configuration memory cells.
Thus, there is a need to reduce the manufacturing cost of FPGA devices.